Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Generic

Used to parameterize a design entity. Different Instances of the same design entity can have different values for the generic parameters. Generics are given values in the generic map of an Instance.

Syntax

  generic (GenericName, ... : DataType [:= Expression];
           ...);
    

Where

entity-is--port-end component--port-end block--generic map-port-begin-end

Rules

The Expression gives the default value, and must be static. Only a generic with a default value can be omitted from the corresponding generic map. Generics are constants; they cannot be assigned new values.

Things to remember

The generics of an entity must be duplicated in the corresponding component, to allow instances of the component to be configured implicitly via the default rules.

Synthesis

Many synthesis tools support only integer generics.

Example

  generic (N, M: Positive;
           Mask: Std_logic_vector := "11111111");
    

See Also

Generic map, Entity, Component, Port